claude

dv-netlist-equivalence

Prove that a refactored Xilinx ISE/XST design synthesizes to equivalent logic: a validated register-cut-point checker for flat netgen Verilog netlists (exhaustive and BDD comparison, exact register correspondence) plus a mutant generator to validate the checker first.

0 on GitHubby BarabashkaDv0.1.0Apache-2.0updated 6 days agoengineering
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Plugin dv-netlist-equivalence from marketplace dv-claude-dev-market in BarabashkaD/dv-claude-dev-market. Commands read from the repo's manifest — 6 days ago.

What it installs

Skills (1)

  • proving-netlist-equivalence

    Use when a refactored Xilinx ISE/XST design must be shown to synthesize to unchanged logic - the bitstream changed after a hierarchy change, module move, wrapper or rename; no Conformal, Formality or Yosys equivalence flow is available; netgen Verilog netlists of both .ngc files can be produced; or

View source on GitHub

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