jitx

JITX workflow skills for PCB design. Use jitx-project-builder to turn board requirements into a complete, verified design through phased sub-agent work. Use jitx-component-modeler for component creation from datasheets. Use jitx-circuit-builder for wiring circuits, passives, and application circuits. Use jitx-substrate-modeler for capturing information about the fabrication substrate. Use jitx-code-layout to write a fixed layout in code: relative placement, code-placed vias, code routes and narrowing, length matching, pours, keepouts, copper and overlappable copper (antennas, filters, net ties), and reading the realized layout back. Use jitx-interactive-layout for placing and routing in the open layout from scripts through jitx design session and exec, so the result stays editable in the board editor, and for reading back route status, issues and skew margins. Use jitx-layout-constraints for design rules, clearances, classes of nets by tag, power trace width, pour rules, via stitching and fencing, routing structures applied by tag, and fanout step-down into package pads. Use jitx-interconnect-constraints for signal integrity constraints (timing, skew, insertion loss), pin models, differential pairs, daisy-chain topology, and protocol-level constraint patterns. Use jitx-pin-assignment for pin assignment patterns including provide/require, pin muxing, DiffPair P/N swapping, PCIe lane ordering, DDR byte/bit swapping, and SI constraints on pin-assigned ports. Use jitx-code-review for same-model self-critique of JITX Python code against the anti-string-hacking architectural rules — mandatory for complete-board tier at task acceptance, user-invoked for single-task work. Use jitx-mechanical for mechanical CAD import/export through the jitx-mechanical CLI, Model3D STEP attachment, and board STEP export guidance. Use jitx-jlcpcb, the opt-in JLCPCB fab option, only once the user has chosen JLCPCB: its predefined substrates, LCSC parts and assembly tiers, catalogue footprints,

13 skills