AMD Ross Agentic AI Assistant

Plugin amd-ross-agentic-ai-assistant from marketplace amd-ross-agentic-ai-assistant in Xilinx/ross-ai-assistant. Commands read from the repo's manifest — 19 days ago.

Skills (50)

• hls-architect

  Convert input code to a multi-stage HLS dataflow, validate with the other hls skills, then hand off to optimize.

• hls-array-to-stream

  Analyze whether a given C/C++ code snippet follows the recommended coding style for array-to-stream conversion in Vitis HLS. Keywords: array, stream, HLS, pragma, ap_fifo, axis, interface

• hls-burst-inference

  Analyze whether burst inference optimization can be applied to a given C/C++ code snippet in Vitis HLS. Keywords: burst, HLS, pragma, m_axi, AXI, memory, optimization

• hls-component-basic-info

  Get Vitis HLS component basic informations for a given HLS component. The basic informations includes component name, source files, testbench files, include paths and top function

• hls-cosim-report

  Get Vitis HLS cosimulation report information for a given HLS component.

• hls-dataflow-infos

  Get Vitis HLS dataflow process/channel informations for a given HLS component.

• hls-dataflow

  Analyze whether a given C/C++ code snippet contains a canonical dataflow region for Vitis HLS. Keywords: dataflow, HLS, pragma, canonical, stream, PIPO, hls::task

• hls-flattenable

  Analyze whether a given C/C++ code snippet contains a flattenable loop nest for Vitis HLS.

• hls-ii-diagnose

  Diagnose the root cause of an II (initiation interval) violation in a synthesized Vitis HLS component, classify the bottleneck, and cite the supporting evidence — without modifying source or running flows.

• hls-impl-report

  Get Vitis HLS implementation report information (post-route clock, resource utilization,Fail Fast table gives utilization percentages) for a given HLS component.

• hls-line-buffer

  Fill the HLS line-buffer and window-buffer gap for stencil kernels, including TOTAL_ITER drain and verification. Use when generated buffer code misses the drain or the check.

• hls-matlab-to-cpp

  Convert MATLAB sample-based code to plain C++ frame-based loops — analyze algorithm, generate C++ that compiles with g++, verify against MATLAB golden, then hand off to /hls-architect for HLS dataflow architecture.

• hls-optimize

  Iteratively optimize the HLS kernel against a given criteria (e.g. minimize latency, reduce DSP usage, maximize throughput) by applying and measuring pragma and algorithmic changes.

• hls-perf-pragma

  Vitis HLS Performance Pragma — calculate target_ti from a throughput target, cascade through architecture and loops, and present the pragma placement table for user confirmation. Run this before placing any #pragma HLS performance.

• hls-pipe-decomp

  Decompose a Vitis HLS pipelined region that accesses many streams into a linear chain of smaller sub-pipelines inside a dataflow region, to reduce pipeline-control complexity and improve timing. Keywords: pipeline, dataflow, stream, FIFO, timing, frequency, split pipeline, decompose

• hls-pipeline

  Guide users on how to apply pipeline pragma in C/C++ regions, analyze region validity for pipelining, and configure II, rewind, and style options

• hls-pragma-scope

  Defines HLS pragma scope rules. Must be referenced when analyzing HLS designs or generating any code for HLS designs to ensure pragmas are placed in the correct scope.

• hls-run-flow

  Run HLS Flow including C Simulation (csim), C Synthesis (csynth), C/RTL Co-Simulation (cosim), Implementation (impl).

• hls-stencil-pattern

  Analyze whether stencil pattern optimization can be applied to a given C/C++ code snippet in Vitis HLS. Keywords: stencil, HLS, pragma, array_stencil, window, optimization

• hls-synth-report

  Get Vitis HLS synthesis report information (synth report, pragma report, and filtered synthesis log) for a given HLS component.

• hls-synthesizable

  Analyze whether user code is synthesizable for HLS

• hw-ila-debug

  Interact with ILA debug cores via vivado-mcp or chipscope-mcp. Discover cores, configure triggers, arm, capture, upload, export waveform data (CSV/VCD), and analyze results. ILA in vivado-mcp supports every device family supported by Vivado. chipscope-mcp supports Versal only. Use when user asks to

• hw-vio-debug

  Interact with VIO debug cores via vivado-mcp or chipscope-mcp. Read input probes, drive output probes, monitor activity, and reset outputs. vivado-mcp supports all device families. chipscope-mcp supports Versal only. Use when user asks to "read VIO inputs", "drive VIO output", "assert <signal> via V

• segcfg-aie

  Guide AI Engine (AIE) integration with Segmented Configuration. Use when designing or building a Versal design that includes AI Engines alongside Segmented Configuration, covering XSA export, PDI packaging, Vitis v++ hardware and emulation flows, and xclbin metadata.

• segcfg-design-check

  Run Segmented Configuration DRCs and pr_verify design verification checks. Use when validating a design for IO bank conflicts, clocking issues, DDRMC sharing violations, or when comparing routed checkpoints for PL reload compatibility.

• segcfg-design-considerations

  Understand Segmented Configuration design constraints for IO banks, CPM/PCIe use cases, and Gen 2 device-specific features (VCU, ISP, ASU, DPDC, 10GbE). Use before finalizing a design that straddles PS and PL domains.

• segcfg-dfx

  Explain how Segmented Configuration interacts with Dynamic Function eXchange (DFX) on AMD Versal devices. Use this if someone asks about using DFX with Segmented Configuration.

• segcfg-hw-manager

  Program Versal hardware using Vivado Hardware Manager in Segmented Configuration mode. Use when programming boot.pdi and pld.pdi through the Vivado GUI, programming configuration flash memory, or enabling the segmented configuration dialog for first-generation Versal devices.

• segcfg-overview

  Explain Segmented Configuration concepts for AMD Versal devices — what it is, why it exists, the two-phase boot model, supported device families, and how it compares to standard boot. Use this if someone asks what Segmented Configuration is, how it works, or whether it applies to their device.

• segcfg-pl-reload

  Guides the Versal Segmented Configuration PL reload workflow for creating and validating multiple independently compiled `pld.pdi` variants while keeping `boot.pdi` fixed. Use when a user asks how to set up a golden PL reload design, spawn a new PL variant project, preserve NoC boot paths with `writ

• vai-aie-compiler-oriented-optimizations

  Performance optimization guide for custom AIE kernel development with Peano. Covers restrict pointers, DM bank annotations, loop pragmas, loop hints, software pipelining (pre-RA vs post-RA), loop versioning, function structure, pointer increments, sub-32-bit limitations, vector alignment, type conve

• vai-aie-kernel-development

  Comprehensive AIE kernel development guide covering architecture-level

• vai-custom-op-candidates

  Find customOperator optimization chains and their ONNX node boundaries

• vai-custom-op-implementation

  End-to-end custom AIE operator development for VAIML: extract a subgraph

• vai-custom-op

  Orchestrate multi-agent parallel development of multiple custom AIE operators

• vai-dequantize-model

  Strip quantization from an ONNX model to produce a non-quantized (float)

• vai-fe-args

  Determine the correct fe_args and vaiml_config flags for a mixed-precision

• vai-ffn-quantization

  Identify and quantize Feed-Forward Network (FFN) layers in ONNX models.

• vai-flag-configuration

  Iteratively improve the VAIML compilation configuration for an ONNX model.

• vai-partition-analysis

  Inspect the result of a VAIML compilation of a mixed-precision ONNX model

• vai-peak-bandwidth-analysis

  From L3 DDR DMA-channel profiling, judge compute- vs memory-bound execution

• vai-perf-analysis

  Analyze performance of VAIML compiled models. Uses the AI Analyzer SDK

• vai-quantization-guide

  Master orchestrator for mixed-precision ONNX model quantization targeting

• vitis-embedded

  Build the Vitis embedded software lifecycle end to end — create an embedded hardware platform, create a standalone/FreeRTOS/Linux application on that platform, and package a bootable image (BOOT.BIN / PDI via Bootgen). Works INSIDE the Vitis Unified IDE's AI agent via the `runVitisPython` tool again

• vivado-ip-configurator

  Use this skill for configuring ANY Vivado IP block via natural language. Trigger whenever the user asks to configure, customize, parameterize, or set up an IP core — including AXI peripherals, processing systems (Zynq PS, Versal CIPS), memory controllers, DSP blocks, clocking, resets, DMA, interconn

• vivado-revision-control

  Comprehensive Vivado project revision control strategies for standard, DFX (Partial Reconfiguration), IPI Block Design Container, and Segmented Configuration projects. Includes automated tools for project type detection, source analysis, settings capture, and build script generation. Use this skill

• vivado-rtl-elaboration-analysis

  Analyze Vivado Oasys synthesis elaboration errors, critical warnings, and warnings from synthesis logs and provide actionable RTL code fixes. Log analysis is the primary mode; an active Vivado session is secondary. Inspect the user's actual RTL at every reported file and line before proposing a fix.

• vivado-rtl-lint

  Run Vivado's RTL linter to detect design issues before synthesis. Use when user asks to "lint RTL", "check HDL code", "run linter", "find RTL issues", or "check design quality". This skill ONLY analyzes the report generated by the RTL linter command.

• vivado-simulate-rtl

  Runs and diagnoses FPGA RTL simulations through Vivado using XSim, Questa, ModelSim, VCS, Xcelium, Riviera-PRO, or Active-HDL; supports approval-gated interactive repair; creates self-checking testbenches; runs UVM and seeded regressions; closes XSim code and functional coverage; verifies assertions

• vivado-timing-methodology-checks

  Runs 55+ timing methodology checks (UG906) on synthesized FPGA designs to identify timing violations and generate actionable RTL/XDC fixes. Make sure to use this skill whenever user mentions: "timing methodology", "methodology checks", "methodology report", "report_methodology", "UG906", "fix timing

Subagents (3)

• README
• vai-custom-op-worker

  Thin worker agent that develops one custom AIE operator by running the vai-custom-op-implementation skill (Phases 1-5) inside a single assigned hermetic workspace, then returns a structured report to the orchestrator.

• vai-mixed-precision-worker

  Worker agent for mixed-precision quantization tasks. Executes specific sub-tasks assigned by the orchestrator: quantization, dequantization, patching, compilation, or accuracy evaluation. Works within defined scope defined by team leader and reports structured results. Must ask leader before broaden

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