claude

fpga

Explain and review existing AMD/Xilinx FPGA projects with drill-down Vivado-style diagrams and clock-domain, constraint and overlay checks.

28 on GitHubby Abdullah AlNafisahv0.2.0MITupdated 12 days agodevelopment
/

Plugin fpga from marketplace fpga-project-analyzer in al-nafisah/fpga-project-analyzer. Commands read from the repo's manifest — 12 days ago.

What it installs

Skills (4)

  • debug

    Find why an FPGA build failed (Vivado, HLS, PetaLinux) and how to fix it.

  • explain

    Explain an FPGA project (Vivado, Zynq, PYNQ) with an interactive drill-down diagram.

  • fpga-project-analyzer

    Analyze and explain existing AMD/Xilinx FPGA projects visually - Vivado block designs (.xpr, .bd, .hwh, .xsa, BD Tcl), Verilog/SystemVerilog/VHDL, PYNQ overlays and notebooks, HLS/bare-metal C, device trees, timing/DRC reports and build logs. Builds a drill-down Vivado-style diagram (block design ->

  • review

    Review an FPGA project for hardware bugs - clock-domain crossings, pins, resets, address map, PYNQ overlay mistakes.

View source on GitHub al-nafisah.github.io

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