gateflow

Plugin gateflow from marketplace gateflow in codejunkie99/Gateflow-Plugin. Commands read from the repo's manifest — 1 month ago.

Skills (27)

• gf-architect

  Codebase architect - Maps and documents SystemVerilog projects. This skill should be used when the user wants to understand a codebase structure, generate architecture documentation, or onboard to a new RTL project. Example requests: "map this codebase", "document the architecture", "show module hie

• gf-build

  Parallel build orchestrator for SystemVerilog creation tasks. Decomposes designs into independent modules, builds in parallel phases, runs verification on each component, then integrates. Example: "/gf-build RISC-V CPU with ALU, regfile, decoder, control FSM" - Read - Write - Edit - Glob - Grep - Ba

• gf-cocotb

  Python-based testbench generation using Cocotb. Alternative to SystemVerilog testbenches for Python-native hardware engineers. Example: "create a cocotb test for the FIFO", "write Python testbench" - Bash - Read - Write - Glob - Grep - Task - AskUserQuestion

• gf-errors

  Error translation layer for hardware tool outputs. Converts cryptic Verilator, Yosys, GHDL, and simulation errors into 3-layer explanations. Used internally by gf orchestrator — not user-invocable directly.

• gf-expand

  Expand mode - asks clarifying questions, presents options with trade-offs, then hands off to appropriate skill/agent with enriched context. - Read - Glob - AskUserQuestion - Skill - Task

• gf-formal

  Formal verification from natural language. Generates SVA properties, configures SymbiYosys, runs proofs, and explains results. Example: "formally verify the FIFO never overflows" - Bash - Read - Write - Glob - Grep - Task - WebSearch - AskUserQuestion

• gf-fusesoc

  FuseSoC build system integration for GateFlow. Generates .core files and drives synthesis/simulation through Edalize backends (Vivado, Quartus, open-source tools). Use when the user needs to create a FuseSoC core file, build with Edalize, or integrate RTL into a FuseSoC project.

• gf-ip-detect

  Auto-detect IP blocks within FPGA and hardware codebases. Scans for module instantiations, identifies missing implementations, matches standard IP patterns, and dispatches agents to fill gaps. Example: "scan for missing IP blocks", "detect what needs implementing", "find unimplemented modules", "aut

• gf-ip

  IP block library manager. Install, list, and query verified drop-in hardware components. Each block includes RTL, testbench, formal properties, and documentation. Example: "add a FIFO to my project", "/gf-ip add uart" - Bash - Read - Write - Glob - Grep

• gf-learn-ctx

  Contextual learning — micro-lessons embedded in workflow output. Explains hardware concepts on first encounter, tracks what has been taught, generates practice exercises on demand. Used internally by orchestrator — not typically invoked directly.

• gf-learn

  SystemVerilog learning mode — generates exercises, reviews solutions, and teaches RTL design patterns. Use when the user wants to learn SystemVerilog, practice hardware design, get exercises, or understand verification methodology.

• gf-lint

  SystemVerilog lint checker with structured output for orchestration. Runs Verilator lint, categorizes errors/warnings, explains issues, and returns a parseable result block for /gf orchestration. - Bash - Read - Glob

• gf-pcb

  KiCad schematic and PCB generation from natural language. AI-verified drafts with DRC/ERC/AI review loop. Example: "design a breakout board for iCE40 with SPI flash and 2 PMODs" - Bash - Read - Write - Glob - Grep - Task - WebSearch - WebFetch

• gf-pinmap

  Board-aware pin mapping. Generates FPGA constraint files (.xdc/.pcf/.lpf/.cst) with correct pin assignments, I/O standards, and drive strength for target boards. Example: "map SPI to PMOD JA on Arty A7", "generate constraints for my iCEBreaker" - Bash - Read - Write - Glob - Grep - Task - WebSearch

• gf-plan

  Hardware design planner - Creates comprehensive RTL implementation plans. This skill should be used when the user wants to plan a new design, architect a complex feature, or understand how to implement hardware before coding. Example requests: "plan a DMA controller", "design a UART", "architect the

• gf-pnr

  Place and route with nextpnr for open-source FPGA targets. Supports iCE40, ECP5, and Gowin devices. Example: "place and route for iCEBreaker", "run P&R targeting ice40" - Bash - Read - Write - Glob - AskUserQuestion

• gf-project

  Manages .gateflow/project.yaml for project-specific configuration. Auto-detects project settings or prompts user for board, HDL, and target. Used internally by other skills — not typically invoked directly.

• gf-protocols

  Protocol scaffolding library. Generates correct, readable protocol interface scaffolds (AXI4-Lite, SPI, UART, I2C, AXI4-Full, AXI-Stream, Wishbone) with testbench templates and integration examples. Example: "create an I2C master interface", "scaffold AXI-Stream source" - Read - Write - Glob - Grep

• gf-release

  GateFlow release readiness workflow. Validates plugin manifests, marketplace metadata, docs index coverage, root mirrors, release notes, and component counts before a version tag is created. Use when preparing, checking, or cutting a GateFlow plugin release. - prepare GateFlow release - cut a GateFl

• gf-router

  Figures out what kind of digital hardware design task the user wants to do, then hands off to the right specialist. Use when the request is unclear, multi-step, or needs help deciding whether to simulate, synthesize, lint, or implement.

• gf-sim

  SystemVerilog simulator with structured output for orchestration. Auto-detects DUT vs testbench, compiles with Verilator, runs simulation, and returns a parseable result block for /gf orchestration. - Bash - Read - Glob - Grep

• gf-summary

  Summarize Verilator, lint, or simulation output into a readable, actionable format. Use when the user wants to understand build output, lint errors, or simulation results from a Verilator or EDA tool run.

• gf-synth

  Synthesize SystemVerilog/Verilog with Yosys. Reports area, timing, and resource utilization. Warns about unsupported SV constructs. Example: "synthesize my design for iCE40" - Bash - Read - Write - Glob - Grep - Task

• gf-tui

  GateFlow terminal console inspired by OpenClaw local TUI workflows. Shows workspace status, component inventory, tool health, map readiness, release readiness, and command shortcuts from one terminal surface. - open GateFlow TUI - show GateFlow dashboard - terminal console - CLI TUI - OpenClaw-style

• gf-viz

  Terminal visualization for GateFlow codebase maps. Renders module hierarchies, FSM state diagrams, and module detail cards as interactive ASCII/Unicode art. Example requests: "visualize the codebase", "show hierarchy", "show FSM", "show module detail" - Read - Glob - Grep - Task - AskUserQuestion

• gf

  Primary SystemVerilog/RTL orchestrator for GateFlow. Routes to specialist agents, runs verification, and iterates until working. Use when the user wants to create, test, fix, or implement any RTL design — FIFO, UART, AXI, state machines, or any digital hardware module.

• tb-best-practices

  Testbench verification best practices and patterns. This skill should be used when the user needs testbench architecture guidance, verification methodology, or wants to write professional-quality testbenches. Example requests: "testbench best practices", "how to structure TB", "verification patterns

Slash commands (21)

• /gateflow:gf-audit

  Audit plugin quality and optionally auto-fix issues

• /gateflow:gf-boards

  List supported boards and query pinouts

• /gateflow:gf-cocotb

  Generate Python testbench using Cocotb

• /gateflow:gf-demo

  One-command demo - generates, lints, and simulates a working project

• /gateflow:gf-detect

  Scan codebase for missing IP blocks, stubs, and CDC issues

• /gateflow:gf-doctor

  Env check

• /gateflow:gf-fix

  Fix lint

• /gateflow:gf-flash

  Flash bitstream to FPGA board

• /gateflow:gf-formal

  Run formal verification

• /gateflow:gf-fusesoc

  Generate FuseSoC .core file for the project

• /gateflow:gf-gen

  Generate scaffolds

• /gateflow:gf-ip

  Manage IP block library

• /gateflow:gf-lint

  Run lint

• /gateflow:gf-map

  Map codebase

• /gateflow:gf-pcb

  Generate KiCad schematic and PCB (AI-verified draft)

• /gateflow:gf-pinmap

  Generate pin constraint file for target board

• /gateflow:gf-pnr

  Run place and route

• /gateflow:gf-release

  Validate GateFlow plugin readiness and prepare a versioned release

• /gateflow:gf-scan

  Index project

• /gateflow:gf-sim

  Run sim

• /gateflow:gf-tui

  Open the GateFlow terminal console

Subagents (20)

• gf-auditor

  Plugin quality auditor — scans the entire GateFlow plugin for gaps, inconsistencies, missing features, stale content, and improvement opportunities. Produces a prioritized report with actionable fixes. Example: "audit the plugin", "what's missing", "find gaps in GateFlow" - Read - Glob - Grep - Bash

• gf-pluginfixer

  Plugin hole-plugger — takes audit findings and automatically fixes gaps, stubs, inconsistencies, and missing content across the plugin. Works as a sub-agent that receives issues and implements fixes. Example: "fix all plugin gaps", "plug the holes", "auto-fix audit findings" - Read - Write - Edit -

• pcb-designer

  KiCad schematic and PCB generation specialist. Creates AI-verified draft schematics and PCB layouts with self-improving verification loop. Example requests: "design a breakout board for iCE40", "create schematic for FPGA dev board" - Read - Write - Bash - Glob - Grep - WebSearch - WebFetch

• sv-codegen

  SystemVerilog RTL architect - Creates synthesizable modules and hardware blocks. This agent should be used when the user wants to create new SystemVerilog modules, implement FSMs, FIFOs, arbiters, pipelines, or any RTL design from scratch. Example requests: "create a FIFO module", "write an FSM for

• sv-debug

  RTL debug specialist - Diagnoses simulation failures and unexpected behavior. This agent should be used when the user has simulation issues, X-value propagation, timing problems, or code that doesn't work as expected. Example requests: "why is my output X", "simulation is stuck", "debug this failure

• sv-developer

  Full-stack RTL developer - Handles complex multi-file implementation tasks. This agent should be used when the user has a large feature requiring multiple files, architectural changes, or coordinated modifications across the codebase. Example requests: "implement the memory subsystem", "add DMA supp

• sv-formal

  Formal verification specialist - Generates SVA properties from natural language and configures SymbiYosys proofs. This agent should be used when the user wants to formally verify properties, prove correctness, or find counterexamples. Example requests: "prove the FIFO never overflows", "formally ver

• sv-ip-scanner

  IP block scanner and auto-filler. Analyzes hardware codebases to detect missing modules, identify standard IP patterns, find CDC violations, and generate implementations. Works as a skill that other agents can invoke. Example: "scan for missing IP", "what modules need implementing", "find and fill I

• sv-orchestrator

  Parallel RTL orchestrator - Decomposes designs into components and builds them in parallel. This agent is the **default build engine** after planning, even for single-module tasks (single-module = one component in Phase 1). Example requests: "build a RISC-V CPU", "create a complete SoC", "implement

• sv-pinmap

  Pin assignment specialist - Generates FPGA constraint files with correct pin mappings, I/O standards, drive strength, and slew rate for target boards. Example requests: "map SPI to PMOD JA on Arty A7", "generate constraints for iCEBreaker" - Read - Write - Bash - Glob - Grep - WebSearch - WebFetch

• sv-planner

  SystemVerilog planning agent - asks clarifying questions and produces a detailed RTL architecture plan before any coding. Use for requests like "plan a DMA", "design a UART", "architect a subsystem", or "how should I implement X". - Read - Glob - AskUserQuestion - Write - WebFetch

• sv-refactor

  Code quality engineer - Refactors, optimizes, and fixes SystemVerilog code. This agent should be used when the user wants to clean up code, fix lint warnings, improve coding style, or optimize existing RTL. Example requests: "fix these lint errors", "refactor this module", "clean up the code style"

• sv-synth

  Synthesis optimization specialist - Runs Yosys synthesis, reports area/timing, and helps with synthesis-specific issues like unsupported constructs. Example requests: "synthesize my design", "what's the area estimate", "optimize for fewer LUTs" - Read - Write - Bash - Glob - Grep

• sv-testbench

  Verification engineer - Creates testbenches and simulation environments. This agent should be used when the user wants to write testbenches, create test stimulus, add self-checking logic, or build verification infrastructure. Example requests: "write a testbench for the ALU", "create tests for my FI

• sv-tutor

  SystemVerilog tutor - reviews solutions, gives hints, teaches concepts

• sv-understanding

  RTL analyst - Explains and documents SystemVerilog code architecture. This agent should be used when the user wants to understand existing code, trace signal flows, analyze FSM behavior, or get architectural explanations. Example requests: "explain this module", "how does this FSM work", "trace the

• sv-verification

  Verification methodologist - Adds assertions, coverage, and formal properties. This agent should be used when the user wants to add SVA assertions, functional coverage, cover properties, or formal verification constraints. Example requests: "add assertions for the handshake", "create coverage for FS

• sv-viz

  Terminal visualization agent - Renders interactive ASCII/Unicode diagrams of RTL architecture. This agent should be used when the user wants to explore codebase visualizations interactively, navigate between hierarchy views, FSM diagrams, and module detail cards. Example requests: "visualize the cod

• vhdl-codegen

  VHDL code generation specialist - Creates synthesizable VHDL entities and architectures. This agent should be used when the user wants to create new VHDL modules, implement FSMs, FIFOs, or any RTL design in VHDL. Example requests: "create a VHDL counter", "write a VHDL UART", "generate VHDL entity"

• vhdl-testbench

  VHDL testbench specialist - Creates VHDL testbenches and simulation environments. This agent should be used when the user wants VHDL testbenches, stimulus generation, or verification infrastructure in VHDL. Example requests: "write a VHDL testbench for the counter", "create VHDL test stimulus" - Rea

Hooks (6)

• SessionStart

  ${CLAUDE_PLUGIN_ROOT}/hooks/scripts/check-dependencies.sh

• SessionStart

  ${CLAUDE_PLUGIN_ROOT}/hooks/scripts/session-tracker.py

• UserPromptSubmit

  ${CLAUDE_PLUGIN_ROOT}/hooks/scripts/userpromptsubmit-sv-nudge.py

• PreToolUse

  ${CLAUDE_PLUGIN_ROOT}/hooks/scripts/pretooluse-bash-guard.py

• PostToolUse

  ${CLAUDE_PLUGIN_ROOT}/hooks/scripts/posttooluse-sv-lint-nudge.py

• Stop

  ${CLAUDE_PLUGIN_ROOT}/hooks/scripts/stop-hook.sh

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