ee-skills

Plugin ee-skills from marketplace ee-skills in fxp/ee-skills. Commands read from the repo's manifest — 19 days ago.

Skills (14)

• ee-analog

  Sourced best-practice rules for precision/low-noise analog: error and noise budgets, op-amp stability, ADC drivers and anti-alias filters, reference routing, bridge/load-cell front-ends (HX711-class), shunt current sensing with Kelvin connections (INA199-class), guard rings and leakage, AGND/DGND. U

• ee-audio

  Sourced best-practice rules for audio circuits: codec/ADC/DAC signal chains, AC-coupling capacitor dielectric and distortion, op-amp stability with capacitive loads, ground partitioning and return currents, Class-D output filters and layout, I2S clocking, THD+N/SNR verification. Use for microphone,

• ee-catalog-maintain

  Add, fix, audit or extend the sourced EE best-practice rule catalog (catalog/*.yaml) - write a rule with quantified parameters and verify methods, validate it, regenerate the domain skills and docs, check source URLs, and audit numbers against their sources. Use when the user wants to add a best pra

• ee-design-review

  Review a schematic, PCB layout, netlist or design spec against a sourced catalog of 500+ circuit-design best-practice rules organised by design stage (architecture, schematic, netlist, placement, routing, planes, manufacturing, sign-off) and by vertical (RF, power, low-power, audio, precision analog

• ee-dfm

  Sourced best-practice rules for DFM/DFA/DFT: fab limits (trace/space, drill, annular ring, mask, silkscreen), JLCPCB capabilities and quirks, panelisation, fiducials and tooling holes, pick-and-place spacing, BOM/CPL conventions and rotation offsets, stencil and via-in-pad, test points, Gerber hygie

• ee-emc-esd

  Sourced best-practice rules for EMC/ESD/surge: loop-area and return-path control, edge-rate and clock handling, I/O filtering (ferrites, common-mode chokes), shield and chassis ground, TVS selection and placement, IEC 61000-4-2/-4/-5 immunity, motor/relay noise suppression, pre-compliance checks. Us

• ee-general-pcb

  Sourced best-practice rules for the whole flow of an ordinary mixed-signal MCU board: requirements and part choice, symbol/footprint libraries, schematic, netlist and net classes, stackup, floorplan, placement, routing, planes and copper pours, sign-off. Use first for any PCB design or review, for d

• ee-high-speed

  Sourced best-practice rules for high-speed digital interfaces: USB, Ethernet (RMII/RGMII), DDR, LVDS, MIPI, PCIe, SPI/I2C on long wires; controlled impedance and stackup, differential-pair coupling and skew, length matching, return paths and via transitions, termination, crosstalk, SI simulation. Us

• ee-hv-safety

  Sourced best-practice rules for high-voltage and isolation: creepage and clearance per IEC 60664-1/62368-1/IPC-2221, basic vs reinforced insulation, isolation-barrier layout, slots and cutouts, optocoupler/isolator/transformer/Y-capacitor placement, mains-side spacing and fusing, hipot testing. Use

• ee-low-power

  Sourced best-practice rules for low-power and battery/IoT designs: sleep-current budgets, leakage paths (pull-ups, dividers, ESD diodes, level shifters), load switches and power gating, quiescent-current regulator choice, Wi-Fi/BLE burst loads vs battery resistance, nA-level measurement. Use for bat

• ee-pcb-verify

  Verify a KiCad design headlessly and automatically - ERC, DRC with custom .kicad_dru rules, schematic-vs-PCB netlist diff, BOM export, pcbnew geometry checks, ngspice simulation through KiCad's bundled libngspice - plus a rule-checking harness that maps catalog rule IDs to pass/fail/evidence JSON. U

• ee-power

  Sourced best-practice rules for power circuits: buck/boost/flyback layout (hot loop, switch node, feedback routing), LDO selection and thermal limits (AMS1117-class), motor drivers and MOSFET switching, high-current copper (IPC-2152), reverse-polarity/fuse/TVS input protection, PDN and decoupling. U

• ee-rf

  Sourced best-practice rules for RF and antenna circuits on PCBs: 2.4 GHz module and chip/PCB antenna keep-outs, pi matching networks, controlled-impedance microstrip/CPWG, via fencing and RF grounding, shielding, TX/RX isolation, tuning and verification with a VNA or S-parameter simulation. Use for

• ee-thermal

  Sourced best-practice rules for PCB thermal design: theta-JA/JC/psi-JT and junction-temperature budgets, copper spreading for SOT-223/DPAK parts, thermal vias and exposed-pad land patterns, hot-part placement, trace temperature rise (IPC-2152), MOSFET and LDO dissipation, thermal verification. Use w

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