WaterHand Processor Development Skills

Plugin processor-development-skills in sixblade325/WaterHand-Processor-Development-Skills. Commands read from the repo's manifest — 19 days ago.

Skills (6)

• bootstrap-processor-project

  Initialize or safely upgrade a processor project's root AGENTS.md from a maintained baseline. Use when starting a processor project, adding project-level Agent collaboration rules, or comparing an existing AGENTS.md with the package baseline. This skill only handles AGENTS.md; it does not scaffold d

• design-chisel-processor

  Develop, challenge, and document Chisel processor microarchitecture designs before implementation. Use when discussing or writing design documents for processor pipelines, queues, issue logic, rename, ROB, LSU, caches, MSHRs, forwarding, wakeup, replay, flush, privilege, exceptions, or other cycle-a

• implement-chisel-processor

  Document-driven workflow for implementing, reviewing, and verifying Chisel processor and memory-subsystem RTL. Use when Codex must work from maintained Architecture and Design, trace a complete integration surface, reason in synthesized-hardware terms, keep source-adjacent _codex.md summaries curren

• optimize-chisel-fpga-timing

  Diagnose and optimize timing-critical Chisel RTL for FPGA implementation while preserving cycle semantics. Use for Vivado timing bottlenecks, long ready or admission paths, queue and issue selection, free-list bank mapping, priority encoders, one-hot arbitration, wide muxes, late-arriving forwarding

• organize-processor-docs

  Establish, author, restructure, or audit human-first processor Architecture, Design, Research, Review, and Verification documentation. Use for progressive documentation scaffolding, authority maps, reading paths, document-type content contracts, length-budgeted splitting, or maintainability reviews.

• trace-vivado-timing-to-rtl

  Task-sized forensic analysis of Vivado synthesis and routed timing evidence for processor RTL. Use when Codex must trace a named setup or hold path, audit whole-design timing populations, compare implementation runs, map primitive, LUT, CARRY, BRAM, DSP, MUXF, register, and routed-net stages back to

Similar plugins