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hdldiagZero - JSON-spec-driven SVG block diagrams of HDL/RTL designs.

30 · lcapossio/hdldiagZero1 pluginMITupdated 3 months ago

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hdldiagZero

claude

Generate clean SVG block diagrams of HDL/RTL/SoC designs. Color-codes by clock domain, distinguishes AXI-MM/Lite/Stream, draws CDC blocks with split fill, omits clock/reset/JTAG/debug clutter, and validates output geometry.

1 skill

30

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