claude

hdldiagZero

Generate clean SVG block diagrams of HDL/RTL/SoC designs. Color-codes by clock domain, distinguishes AXI-MM/Lite/Stream, draws CDC blocks with split fill, omits clock/reset/JTAG/debug clutter, and validates output geometry.

30 on GitHubby Leonardo Capossiov1.2.10MITupdated 3 months agofpga
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Plugin hdldiagzero from marketplace hdldiag-marketplace in lcapossio/hdldiagZero. Commands read from the repo's manifest — 19 days ago.

What it installs

Skills (1)

  • hdldiagzero

    Generate validated SVG block diagrams for HDL/RTL/FPGA/SoC designs. Use when asked to draw, diagram, sketch, render, or visualize Verilog, SystemVerilog, VHDL, Vivado BD, or LiteX architecture. Produces JSON specs plus SVGs, color-codes clock domains, distinguishes AXI/MM/Lite/Stream and TileLink, a

View source on GitHub bard0.com

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