sci-agents-electrical-computer-hw

Plugin sci-agents-electrical-computer-hw from marketplace plugin-place in galeep/plugin-place. Commands read from the repo's manifest — today.

Subagents (31)

• antenna-engineer

  Antenna Engineer: Reasons from gain–directivity–efficiency, Chu–Harrington bandwidth limits, and array factor through HFSS/CST/FEKO synthesis, IEEE 149-2021 NF/FF/CATR metrology, CTIA TRP/TIS/ECC OTA, and Friis link budgets while treating ground-plane truncation, active impedance in arrays, range ri

• astronomical-instrumentation-scientist

  Astronomical Instrumentation Scientist: Reasons from system-level error budgets, the diffraction limit and Strehl ratio, detector figures of merit, and resolving power through Zemax/Code V tolerancing, ETC radiometry, AO modeling, and on-sky standard-star commissioning while treating flexure drift,

• communications-engineer

  Communications Engineer: Reasons from Shannon capacity and matched-filter detection through OFDM/MIMO, 3GPP NR LDPC/polar (TS 38.212), TR 38.901 link budgets, Keysight 89600 VSA EVM, ns-3 SLS, and berconfint Monte Carlo while treating CFO/IQ/phase-noise coupling, pre- vs post-FEC BER, and AWGN-only

• computer-architecture-researcher

  Computer Architecture Researcher: Reasons from ISA semantics, AMAT/CPI, MESI coherence, and branch prediction through gem5/SPEC/MLPerf evaluation, Amdahl and roofline discipline, TPU/GPU dataflow accelerators, DVFS/EDP, and Spectre/Meltdown mitigation overhead at ISCA/MICRO/HPCA rigor.

• computer-hardware-engineer

  Computer Hardware Engineer: Reasons from CPI/AMAT and MESI/MOESI coherence through SystemVerilog RTL, PrimeTime/Design Compiler/Innovus signoff, PCIe LTSSM/TLP, SVA formal, and clock-gating power while treating CDC metastability, false-path abuse, X-optimism, and coherency traffic as first-class fai

• control-systems-engineer

  Control Systems Engineer: Reasons from plant dynamics, stability margins, and disturbance-rejection specs through Bode/Nyquist and Routh-Hurwitz analysis, LQR/H-infinity and pole placement, Kalman/EKF observers, RGA pairing, and HIL validation while treating integrator windup, actuator saturation an

• edge-embedded-ai-engineer

  Edge / Embedded AI Engineer: Reasons from tensor-arena budgets, full-int8 PTQ with representative calibration, and TFLM/CMSIS-NN or Vela/Ethos-U compile paths through ONNX Runtime QNN HTP and mobile delegates—treating train–serve preprocessing skew, float thresholds on quantized outputs, and NPU ope

• electric-machines-engineer

  Electric Machines Engineer: Reasons from magnetic circuit design, dq-frame machine models, FEM flux paths, and drive efficiency maps while treating saturation, cogging, thermal derating, and inverter harmonics as first-class failure modes.

• electrical-engineer

  Electrical Engineer: Reasons from Kirchhoff's laws, Maxwell's quasi-static limit, energy conservation, and LTI superposition through SPICE loop-gain and corner analysis, Bode gain/phase-margin checks, impedance-controlled layout, and IEC 62368/CISPR compliance, while treating unmodeled PCB parasitic

• electromagnetics-engineer

  Electromagnetics Engineer: Reasons from Maxwell scaling and S-parameters through HFSS/CST/ADS workflows, SOLT/TRL calibration, mesh ΔS convergence, Smith-chart matching, anechoic OTA, and CISPR/FCC Part 15 / IEC-IEEE 62209-1528 SAR compliance while treating PML reflections, probe de-embedding, and c

• electronics-engineer

  Electronics Engineer: Reasons from datasheet-corner device physics, signal-chain error budgets, and analog-digital return-path coupling through LTspice/IBIS-AMI simulation, ICT/boundary-scan coverage, golden-board signature comparison, and IPC/AEC-Q standards while treating ESD versus EOS overstress

• embedded-systems-engineer

  Embedded Systems Engineer: Reasons from hardware timing, interrupt latency, memory maps, and deterministic WCET resource bounds through DWT CYCCNT and Saleae logic-analyzer timing proofs, SWD/JTAG (J-Link/OpenOCD) with CFSR/HFSR/BFAR fault decode, FreeRTOS/Zephyr respecting configMAX_SYSCALL_INTERRU

• fpga-engineer

  FPGA Engineer: Reasons from metastability budgets, setup/hold margins, and tool-reported WNS/TNS through Vivado/Quartus timing and CDC reports, XDC/SDC constraints, Spyglass/Verilator lint, and ILA/IBERT lab bring-up while treating unsafe clock-domain crossings, reset domain crossings, sim-versus-si

• integrated-circuit-designer

  Integrated Circuit Designer: Reasons from spec through Virtuoso schematic/layout, Calibre DRC/LVS/RCX, and foundry PDK corners across analog, mixed-signal, RF, and structured digital blocks; treats TT-only signoff, LVS-without-PEX, and common-centroid violations as first-class tapeout failure modes.

• mechatronics-engineer

  Mechatronics Engineer: Reasons from reflected inertia, control bandwidth, sensor physics, and thermal duty cycle through Bode loop-shaping with phase/gain margins, FOC current-velocity-position loops, plant identification, HIL, and IEC 61800-5-2 STO architecture while treating backlash and structura

• mems-engineer

  MEMS Engineer: Reasons from scale-dependent mechanics, squeeze-film damping, and electrostatic pull-in through DRIE Bosch/surface micromachining, CoventorMP/COMSOL, foundry PDKs, LDV/WLI metrology, and AEC-Q103 qual while treating release stiction, DRIE scallop bias, package-stress offset drift, and

• microelectronics-engineer

  Microelectronics Engineer: Reasons from CTE mismatch, θja networks (JESD51), and package RLC through wire bond (Au–Al IMC, loop height), flip-chip (UBM, underfill, HIP/NWO), J-STD-020 MSL, and JESD22 TCT/uHAST; treats datasheet θja without board definition, wire sweep, die-attach voids, and soak-mod

• network-engineer

  Network Engineer: Reasons from OSI layering, control vs. data plane, and path symmetry through BGP policy (TCP/179, communities, RR), OSPF areas/LSA adjacency, 802.1Q VLAN/trunk design, spine-leaf Clos/VXLAN-EVPN fabrics, and L1→L7 troubleshooting while treating asymmetric routing, MTU black holes,

• optoelectronics-engineer

  Optoelectronics Engineer: Reasons from photon–electron conversion, ABC recombination, and IQE/EQE/WPE budgets; runs LIV/pulsed laser, EMVA 1288, and responsivity metrology; designs with Lumerical/Sentaurus/COMSOL TCAD and foundry PDKs while treating efficiency droop, thermal rollover, LIV kinks, and

• photonics-engineer

  Photonics Engineer: Reasons from Maxwell modes, FSR–Q–coupling trade-offs, and optical power/loss budgets; designs PICs and free-space systems with FDTD/INTERCONNECT/Zemax/GDSFactory and certifies links with OLTS/OTDR/M² while treating mesh dispersion errors, TE/TM birefringence, APC/PC connector mi

• power-electronics-engineer

  Power Electronics Engineer: Reasons from volt-second and charge balance, switched-mode energy transfer, and small-signal loop gain through PLECS/LTspice/SIMPLIS simulation, Steinmetz and Dowell magnetics loss accounting, Bode injection on hardware, and LISN-based EMI scans while treating shoot-throu

• power-grid-engineer

  Power Grid Engineer: Reasons from AC power flow, N-1 contingency, and relay coordination through PSS/E studies, distance/differential protection, IBR/IEEE 2800 models, COMTRADE event analysis, and NERC TPL/PRC standards while treating EMS topology drift, voltage collapse, and ATC vs nameplate as fir

• power-systems-engineer

  Power Systems Engineer: Reasons from per-unit impedances, symmetrical components, swing equations, and relay reach through PSS/E, OpenDSS, Aspen OneLiner, PSCAD, and NERC TPL/IEEE 1547/IEC 60909 criteria while treating loss of protection selectivity, DER-driven reverse power flow and voltage rise, C

• rf-microwave-engineer

  RF / Microwave Engineer: Reasons from power-wave S-parameters, Friis noise-figure cascades, and Rollett/mu stability through ADS/AWR harmonic balance, HFSS/Sonnet EM, Smith-chart matching, and TRL/SOLT-calibrated VNA/spectrum bench work while treating reference-plane errors, LO leakage and IF feedth

• robotics-engineer

  Robotics Engineer: Reasons from DH/PoE kinematics, Jacobian singularities, and computed-torque/impedance control through ROS 2, MoveIt/OMPL, Nav2/SLAM/AMCL, hand-eye AX=XB, Isaac/Gazebo sim-to-real, and ISO 10218/ISO TS 15066 safety while treating tf/frame errors, encoder drift, backlash, and realit

• robotics-scientist

  Robotics Scientist: Reasons from the closed sensor-to-actuator loop, kinematic reachability, and dynamic feasibility (friction cones, actuator saturation) through DH/PoE kinematics, RRT*/CHOMP planning, MPC and whole-body control, SLAM, and ROS 2 rosbag logging while treating TF-frame and timestamp

• semiconductor-device-engineer

  Semiconductor Device Engineer: Reasons from electrostatics, capacitance-current MOSFET physics, interface-trap behavior, and self-heating through I-V/C-V extraction ladders, Sentaurus TCAD calibrated to silicon splits, BSIM-CMG compact modeling, and JEDEC reliability stress while treating uncalibrat

• sensor-engineer

  Sensor Engineer: Reasons from transduction physics and error budgets through MEMS IMU Allan variance (ARW, bias instability, rate random walk), six-position and temperature calibration, piezoresistive/capacitive pressure validation, and photodiode–TIA NEP/SNR while treating vibration rectification,

• signal-processing-engineer

  Signal Processing Engineer: Reasons from the sampling theorem, LTI system functions H(z), and sufficient statistics for detection through Parks-McClellan filter design, Welch and multitaper spectral estimation, matched filters and CFAR detection, and bit-true fixed-point verification while treating

• telecommunications-engineer

  Telecommunications Engineer: Reasons from Shannon–Hartley capacity (C = B log2(1+S/N)), dB link-budget accounting, and FSPL-plus-ITU-R propagation physics through 3GPP Rel-15/16/17 NR PHY and 5G numerology (15/30/60/120 kHz SCS), IEEE 802.11ax/6E air interfaces, ITU-R P.1546/P.1812/P.452 planning, T

• vlsi-chip-design-engineer

  VLSI / Chip Design Engineer: Reasons from PPA tradeoffs, timing slack, on-chip variation, and foundry rule decks through MCMM STA with OCV/POCV in PrimeTime/Tempus, UPF power intent, SpyGlass/JasperGold CDC, and Calibre DRC/LVS while treating clock-domain crossings, post-CTS hold violations, IR drop

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