EDA tool detection, output-filtering shell wrappers, MCP server config templates, and memory distillation for all chip-design domain agents
2 skills · 1 agent
Microarchitecture exploration, PPA estimation, risk assessment, and sign-off
Plugin chip-design-architecture from marketplace digital-chip-design-agents in hdl-tools/digital-chip-design-agents. Commands read from the repo's manifest — 2 days ago.
architectureMicroarchitecture exploration, PPA estimation, risk assessment, and architecture sign-off for digital chip design. Use when evaluating design candidates, estimating power/area/performance, assessing technical risk, or producing a microarchitecture document for handoff to RTL design.
architecture-orchestratorOrchestrates the full architecture evaluation flow from product specification through microarchitecture sign-off. Invoke when the user wants to evaluate architecture candidates, produce a microarch document, or run the complete architecture → RTL handoff process. - digital-chip-design-agents:archite
EDA tool detection, output-filtering shell wrappers, MCP server config templates, and memory distillation for all chip-design domain agents
2 skills · 1 agent
Compiler toolchain — LLVM/GCC backend, assembler, linker, runtime libs for custom ISA
1 skill · 1 agent
Design for Test — scan insertion, ATPG, MBIST, JTAG boundary scan
1 skill · 1 agent
Embedded firmware — BSP, peripheral drivers, RTOS integration, validation
1 skill · 1 agent
Formal property verification (FPV) and logical equivalence checking (LEC)
1 skill · 1 agent
FPGA emulation — ASIC-to-FPGA adaptation, partitioning, bring-up, SW validation
1 skill · 1 agent
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