EDA tool detection, output-filtering shell wrappers, MCP server config templates, and memory distillation for all chip-design domain agents
2 skills · 1 agent
231
claude
chip-design-dft
Design for Test — scan insertion, ATPG, MBIST, JTAG boundary scan
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Plugin chip-design-dft from marketplace digital-chip-design-agents in hdl-tools/digital-chip-design-agents. Commands read from the repo's manifest — 2 days ago.
What it installs
Skills (1)
dftDesign for Test — scan architecture planning, scan insertion, ATPG pattern generation, MBIST for embedded memories, and JTAG boundary scan. Use when planning a DFT strategy, inserting scan, generating test patterns, or verifying that a chip will be testable in manufacturing.
Subagents (1)
dft-orchestratorOrchestrates the DFT flow from architecture through scan insertion, ATPG pattern generation, BIST, JTAG, and sign-off. Invoke when planning a DFT strategy, inserting scan, generating test patterns, or verifying testability. - digital-chip-design-agents:dft
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