EDA tool detection, output-filtering shell wrappers, MCP server config templates, and memory distillation for all chip-design domain agents
2 skills · 1 agent
231
claude
chip-design-formal
Formal property verification (FPV) and logical equivalence checking (LEC)
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Plugin chip-design-formal from marketplace digital-chip-design-agents in hdl-tools/digital-chip-design-agents. Commands read from the repo's manifest — 2 days ago.
What it installs
Skills (1)
formal-verificationFormal property verification (FPV) and logical equivalence checking (LEC). Use when proving design properties exhaustively, checking RTL vs gate-level netlist equivalence, verifying CDC crossings formally, or closing verification coverage gaps that simulation cannot efficiently reach.
Subagents (1)
formal-orchestratorOrchestrates formal property verification (FPV) and logical equivalence checking (LEC). Invoke when proving design properties exhaustively, checking RTL vs gate-level equivalence, or closing verification gaps with formal methods. - digital-chip-design-agents:formal-verification
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