digital-chip-design-agents

EDA tool detection, output-filtering shell wrappers, MCP server config templates, and memory distillation for all chip-design domain agents

2 skills · 1 agent

Microarchitecture exploration, PPA estimation, risk assessment, and sign-off

1 skill · 1 agent

Compiler toolchain — LLVM/GCC backend, assembler, linker, runtime libs for custom ISA

1 skill · 1 agent

Design for Test — scan insertion, ATPG, MBIST, JTAG boundary scan

1 skill · 1 agent

Embedded firmware — BSP, peripheral drivers, RTOS integration, validation

1 skill · 1 agent

Formal property verification (FPV) and logical equivalence checking (LEC)

1 skill · 1 agent

FPGA emulation — ASIC-to-FPGA adaptation, partitioning, bring-up, SW validation

1 skill · 1 agent

High-level synthesis — C/C++ to RTL, directive optimization, co-simulation

1 skill · 1 agent

Memory IP design — SRAM/register-file/ROM macro selection, array architecture, redundancy and repair, view generation and QA

1 skill · 1 agent

Cross-domain pipeline orchestrator — drives closed-loop verification↔RTL feedback via design_state.json fix_requests, enforcing a 3-iteration cap with user escalation

1 skill · 1 agent

Physical design — floorplan, placement, CTS, routing, timing/power/area opt, sign-off

1 skill · 1 agent

SystemVerilog RTL design — module planning, coding standards, lint, CDC, synthesis check

1 skill · 1 agent

SoC IP integration — procurement, bus fabric, chip-level simulation

1 skill · 1 agent

Static timing analysis — multi-corner analysis, exception review, ECO guidance

1 skill · 1 agent

Logic synthesis — SDC constraints, compile optimization, netlist QC and LEC

1 skill · 1 agent

UVM testbench, test planning, constrained random, coverage closure, regression

1 skill · 1 agent