EDA tool detection, output-filtering shell wrappers, MCP server config templates, and memory distillation for all chip-design domain agents
2 skills · 1 agent
Cross-domain pipeline orchestrator — drives closed-loop verification↔RTL feedback via design_state.json fix_requests, enforcing a 3-iteration cap with user escalation
Plugin chip-design-meta from marketplace digital-chip-design-agents in hdl-tools/digital-chip-design-agents. Commands read from the repo's manifest — 2 days ago.
pipeline-orchestrationCross-domain loop orchestration for the chip design pipeline. Provides the fix_request protocol, iteration-cap logic, escalation templates, and dispatch patterns for routing verification/formal failures to the RTL orchestrator and back. Use when driving the closed-loop verification↔RTL feedback cycl
pipeline-orchestratorCross-domain pipeline orchestrator. Detects open fix_requests in design_state.json, dispatches the RTL orchestrator to apply fixes, then re-runs the originating verification or formal orchestrator. Loops up to 3 cross-domain iterations before escalating to the user via pending_approval. Invoke after
EDA tool detection, output-filtering shell wrappers, MCP server config templates, and memory distillation for all chip-design domain agents
2 skills · 1 agent
Microarchitecture exploration, PPA estimation, risk assessment, and sign-off
1 skill · 1 agent
Compiler toolchain — LLVM/GCC backend, assembler, linker, runtime libs for custom ISA
1 skill · 1 agent
Design for Test — scan insertion, ATPG, MBIST, JTAG boundary scan
1 skill · 1 agent
Embedded firmware — BSP, peripheral drivers, RTOS integration, validation
1 skill · 1 agent
Formal property verification (FPV) and logical equivalence checking (LEC)
1 skill · 1 agent
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