EDA tool detection, output-filtering shell wrappers, MCP server config templates, and memory distillation for all chip-design domain agents
2 skills · 1 agent
231
claude
chip-design-rtl
SystemVerilog RTL design — module planning, coding standards, lint, CDC, synthesis check
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Plugin chip-design-rtl from marketplace digital-chip-design-agents in hdl-tools/digital-chip-design-agents. Commands read from the repo's manifest — 2 days ago.
What it installs
Skills (1)
rtl-designSystemVerilog RTL design — module planning, coding standards enforcement, lint checking, CDC/RDC analysis, and synthesis readiness verification. Use when writing, reviewing, or debugging RTL for ASIC or FPGA targets, or when checking an existing RTL package for synthesis readiness.
Subagents (1)
rtl-design-orchestratorOrchestrates the RTL design flow from module planning through lint-clean, CDC-clean, synthesis-ready sign-off. Invoke when the user wants to design a SystemVerilog block, run lint or CDC analysis, or produce an RTL package ready for synthesis handoff. - digital-chip-design-agents:rtl-design
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