EDA tool detection, output-filtering shell wrappers, MCP server config templates, and memory distillation for all chip-design domain agents
2 skills · 1 agent
231
claude
chip-design-memory-ip
Memory IP design — SRAM/register-file/ROM macro selection, array architecture, redundancy and repair, view generation and QA
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Plugin chip-design-memory-ip from marketplace digital-chip-design-agents in hdl-tools/digital-chip-design-agents. Commands read from the repo's manifest — 2 days ago.
What it installs
Skills (1)
memory-ip-designEmbedded memory IP design — SRAM/register-file/ROM requirements capture, memory compiler and macro selection, array architecture (banking, ports, ECC wrapper), redundancy and repair allocation, view generation and QA, and integration handoff to DFT, PD, and STA. Use when specifying or selecting memo
Subagents (1)
memory-ip-orchestratorOrchestrates the memory IP design flow from memory requirements capture through macro selection, array architecture, redundancy and repair, view generation, and integration sign-off. Invoke when the user wants to specify or select SRAM, register-file, or ROM macros, architect a memory subsystem's ba
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