chip-design-verification

Plugin chip-design-verification from marketplace digital-chip-design-agents in hdl-tools/digital-chip-design-agents. Commands read from the repo's manifest — 2 days ago.

Skills (1)

• functional-verification

  UVM-based functional verification — testbench architecture, test planning, directed and constrained-random stimulus, functional and code coverage closure, formal assist, and regression sign-off. Use when building a UVM testbench, writing tests, analysing coverage, or managing a verification regressi

Subagents (1)

• verification-orchestrator

  Orchestrates the UVM functional verification flow from testbench architecture through coverage-closed regression sign-off. Invoke when building a UVM testbench, running tests, closing coverage, or managing a verification campaign, and when porting an existing testbench to another simulator (VCS, Xce