EDA tool detection, output-filtering shell wrappers, MCP server config templates, and memory distillation for all chip-design domain agents
2 skills · 1 agent
231
claude
chip-design-pd
Physical design — floorplan, placement, CTS, routing, timing/power/area opt, sign-off
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Plugin chip-design-pd from marketplace digital-chip-design-agents in hdl-tools/digital-chip-design-agents. Commands read from the repo's manifest — 2 days ago.
What it installs
Skills (1)
physical-designFull physical design flow — floorplan, placement, clock tree synthesis, routing, timing optimisation, power optimisation, area optimisation, and tape-out sign-off. Use when implementing a gate-level netlist through to GDS-II, closing timing and power, or performing any individual PD stage analysis.
Subagents (1)
physical-design-orchestratorOrchestrates the full physical design flow — floorplan, placement, CTS, routing, timing optimisation, power optimisation, area optimisation, and tape-out sign-off. Invoke when implementing a gate-level netlist to GDS-II or running any individual PD stage. - digital-chip-design-agents:physical-design
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claude & codex plugins16 plugins