EDA tool detection, output-filtering shell wrappers, MCP server config templates, and memory distillation for all chip-design domain agents
2 skills · 1 agent
231
claude
chip-design-soc
SoC IP integration — procurement, bus fabric, chip-level simulation
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Plugin chip-design-soc from marketplace digital-chip-design-agents in hdl-tools/digital-chip-design-agents. Commands read from the repo's manifest — 2 days ago.
What it installs
Skills (1)
soc-integrationSoC IP integration — IP procurement and qualification, IP configuration, bus fabric setup, top-level RTL integration, and chip-level simulation. Use when assembling a SoC from multiple IP blocks, configuring an AXI bus interconnect, integrating memory macros, or running chip-level tests.
Subagents (1)
soc-integration-orchestratorOrchestrates SoC IP integration — IP procurement and qualification, IP configuration, bus fabric setup, top-level RTL integration, and chip-level simulation sign-off. Invoke when assembling a SoC from multiple IP blocks, configuring memory maps, or running chip-level integration tests. - digital-chi
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