EDA tool detection, output-filtering shell wrappers, MCP server config templates, and memory distillation for all chip-design domain agents
2 skills · 1 agent
231
claude
chip-design-synthesis
Logic synthesis — SDC constraints, compile optimization, netlist QC and LEC
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Plugin chip-design-synthesis from marketplace digital-chip-design-agents in hdl-tools/digital-chip-design-agents. Commands read from the repo's manifest — 2 days ago.
What it installs
Skills (1)
logic-synthesisLogic synthesis from RTL to gate-level netlist — SDC constraint validation, compile and optimisation strategy, netlist quality check, and LEC equivalence verification. Use when synthesising RTL for ASIC, setting up timing constraints, optimising for timing/area/power, or verifying a post-synthesis n
Subagents (1)
synthesis-orchestratorOrchestrates logic synthesis from RTL to verified gate-level netlist — SDC constraint validation, compile exploration and final compile, netlist quality check, and LEC equivalence verification. Invoke for synthesis runs or constraint setup and validation. - digital-chip-design-agents:logic-synthesis
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claude & codex plugins16 plugins