EDA tool detection, output-filtering shell wrappers, MCP server config templates, and memory distillation for all chip-design domain agents
2 skills · 1 agent
High-level synthesis — C/C++ to RTL, directive optimization, co-simulation
Plugin chip-design-hls from marketplace digital-chip-design-agents in hdl-tools/digital-chip-design-agents. Commands read from the repo's manifest — 2 days ago.
hlsHigh-Level Synthesis — C/C++ algorithm analysis, HLS directive optimisation, synthesis execution, and co-simulation verification. Use when converting C/C++ to synthesisable RTL, optimising for latency/throughput/area targets using pragmas, or verifying that generated RTL matches the golden C model.
hls-orchestratorOrchestrates High-Level Synthesis — C/C++ algorithm analysis, directive optimisation, synthesis, RTL QC, and co-simulation verification. Invoke when converting C/C++ algorithms to RTL or optimising HLS output for latency, throughput, or area targets. - digital-chip-design-agents:hls
EDA tool detection, output-filtering shell wrappers, MCP server config templates, and memory distillation for all chip-design domain agents
2 skills · 1 agent
Microarchitecture exploration, PPA estimation, risk assessment, and sign-off
1 skill · 1 agent
Compiler toolchain — LLVM/GCC backend, assembler, linker, runtime libs for custom ISA
1 skill · 1 agent
Design for Test — scan insertion, ATPG, MBIST, JTAG boundary scan
1 skill · 1 agent
Embedded firmware — BSP, peripheral drivers, RTOS integration, validation
1 skill · 1 agent
Formal property verification (FPV) and logical equivalence checking (LEC)
1 skill · 1 agent
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