EDA tool detection, output-filtering shell wrappers, MCP server config templates, and memory distillation for all chip-design domain agents
2 skills · 1 agent
231
claude
chip-design-sta
Static timing analysis — multi-corner analysis, exception review, ECO guidance
/
Plugin chip-design-sta from marketplace digital-chip-design-agents in hdl-tools/digital-chip-design-agents. Commands read from the repo's manifest — 2 days ago.
What it installs
Skills (1)
staStatic timing analysis — multi-corner constraint validation, setup and hold analysis, timing exception review, and ECO guidance for closure. Use when running timing analysis on a design, reviewing timing violations, guiding ECO fixes, or performing timing sign-off for tape-out.
Subagents (1)
sta-orchestratorOrchestrates static timing analysis — multi-corner constraint validation, path analysis, timing exception review, ECO guidance, and timing sign-off. Invoke for timing analysis runs, ECO closure guidance, or tape-out timing sign-off. WNS >= 0 and TNS = 0 at all corners required. - digital-chip-design
More from hdl-tools/digital-chip-design-agents
All 16 plugins →chip-design-architecture
claudeMicroarchitecture exploration, PPA estimation, risk assessment, and sign-off
1 skill · 1 agent
231
chip-design-compiler
claudeCompiler toolchain — LLVM/GCC backend, assembler, linker, runtime libs for custom ISA
1 skill · 1 agent
231
chip-design-dft
claudeDesign for Test — scan insertion, ATPG, MBIST, JTAG boundary scan
1 skill · 1 agent
231
chip-design-firmware
claudeEmbedded firmware — BSP, peripheral drivers, RTOS integration, validation
1 skill · 1 agent
231
chip-design-formal
claudeFormal property verification (FPV) and logical equivalence checking (LEC)
1 skill · 1 agent
231
Maintain chip-design-sta?
This page updates itself from your repo. Add the badge to your README, or get it Featured to pin it above the organic results with a followed link to your site.
claude & codex plugins16 plugins